Reymund

FPGA Design Engineer |VHDL|Vivado|Quartus

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Overview

Looking for full-time work (8 hours/day)

at $4.50/hour ($792.00/month)

Bachelors degree

Last Active

November 18th, 2024 (8 days ago)

Member Since

May 17th, 2013

Profile Description

Industry Experience in RTL Design for FPGA and CPLD devicesSkills: Circuit Designer, Hardware Engineer, FPGA RTL CodingLanguage: VHDL and Verilog HDLIDE: Altera Quartus and Xilinx Vivado/ISE
I have used FPGA and CPLD namely: Cyclone III, Cyclone IV, Cyclone V, Stratix II, Stratix V, Max II, Max 10, Virte 6, Virtex 5, Spartan 6, Artix 7, Zynq
Controllers Implemented:PCIe, MIG, ADC, DAC, RAM, FIFO, SPI, I2C, UART, Ethernet etc

Top Skills

Office and Administration » Microsoft Excel

Experience: 5 - 10 years

Office and Administration » Google Sheets

Experience: 5 - 10 years

Professional Services » Construction And Engineering » Circuit Design

Experience: Less than 6 months

Create PCB guidelines for FPGA circuit design and other digital circuits. Create Schematic Design for FPGA and other digital devices.

Other Skills

Office and Administration » Microsoft Power Point

Experience: 5 - 10 years

Office and Administration » Microsoft Word

Experience: 5 - 10 years

Basic Information

Age: 30

Gender: Male

Website: Sign Up with Pro Account to View

Address: Binan, Laguna

Tests Taken: IQ
Score: 107: DISC
Dominance: 44
Influence: 7
Steadiness: 27
Compliance: 23: English
C1(Advanced)

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